There are various popular instruction sets that are used in the industry and are of theoretical importance. Each one has its own usage and advantages. Following are the instruction set architectures:
Get an overview of each of the above Instruction Sets:
Reduced Instruction Set Computer (RISC) is an instruction set architecture (ISA) which has fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).
RISC processors are also used in supercomputers such as Summit, which, as of November 2018, is the world's fastest supercomputer as ranked by the TOP500 project.
Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) which has fewer instructions per program than a Reduced instruction set computer (RISC).
Minimal instruction set computers (MISC) is a processor architecture with a very small number of basic instruction operations and corresponding opcodes.
As a result of this is a smaller instruction set, a smaller and faster instruction set decode unit, and faster operation of individual instructions. The disadvantage is that smaller instruction set always have more sequential dependencies, reducing instruction-level parallelism.
Very long instruction word (VLIW) is an instruction set architectures designed to exploit instruction level parallelism (ILP).
Central processing units (CPU, processor) mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs.
Explicitly parallel instruction computing (EPIC) is an instruction set that permits microprocessors to execute software instructions in parallel by using the compiler, rather than complex on-die circuitry, to control parallel instruction execution.
This was intended to allow simple performance scaling without resorting to higher clock frequencies.
One instruction set computer (OISC) is an abstract machine that uses only one instruction obviating the need for a machine language opcode.
OISCs have been recommended as guides in teaching computer architecture and have been used as computational models in structural computing research.
Zero instruction set computer (ZISC) is a computer architecture based on pattern matching and absence of (micro-)instructions in the classical sense.
These chips are known for being thought of as comparable to the neural networks being marketed for the number of "synapses" and "neurons"
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